\section{SystemC synthesis}
In order to perform experiments with a given computer architecture, it will first have to be implemented 

\subsection{Basic components}
In order to aid the creation process, a number of basic components, often present in system architectures as described in section \ref{sec:sysarch} 

\subsection{Architecture configuration}


\section{Architecture simulation}

\subsection{Process communication}

\subsection{Simulation front-end}

\subsection{Simulation API}


\section{Testing architectures}

\subsection{ISA4-SS}

\subsubsection{SystemC implementation}

\subsubsection{Instruction set implementation}

\subsection{ISA4-PL}

\subsubsection{?Instruction set implementation}

\subsubsection{SystemC implementation}

% OLD
\chapter{OUD}
\section{SystemC synthesis}
Before any simulation can be run, the architecture has to be implemented first. To aid in this process, the framework offers a way to synthesise a SystemC module based on a configuration file. This allows for the abstraction of certain implementational specifics, such as special components used by the simulation framework---some of which will be introduced further in this implementation chapter, without the user having to integrate these specifics manually. The configuration file used by the SystemC synthesis is TOML (Tom's Obvious, Minimal Language) \citep{preston-werner_gedam_2020}. 

A popular mark-up language for purposes like these is XML, used by SIM-PL for example. TOML was chosen instead however 

\section{Architecture simulation}
The basic global organisation of this projects simulation framework is outlined in figure \ref{fig:glob-prog}.

\begin{figure}
    \centering
    \includegraphics[width=0.8\textwidth]{figures/simulator_global.png}
    \caption{Global program design}
    \label{fig:glob-prog}
\end{figure}

\subsection{Process communication}

\subsubsection{Simulation events}

\subsubsection{Application programming interface}

\subsection{Testing architecture}

\subsubsection{Instruction-set architecture}
Before implementation of the testing architecture could commence, an ISA (instruction-set architecture) had to be made. This ISA outlines each of the instructions which has the be supported by the system architecture and the specifications of these instructions; details like instruction word length and instruction argument layout. Since this architecture would primarily be used for testing purposes, the ISA would not have to be as extensive as those for architectures like x86, ARM or MIPS. Therefore, only a few instructions were selected for implementation. The selection was carefully however, to ensure that while the architecture would be basic, its limited instruction-set could theoretically be used to implement somewhat sophisticated assembly programmes. The chosen instructions and their argument layout is shown in table \ref{tab:isa}. 

\begin{table}[]
\centering
\begin{tabular}{lll}
\textit{\textbf{Instruction}} & \textit{\textbf{Op-code}} & \textit{\textbf{Arguments}} \\ \hline
\textbf{add} & 0x0 & \textit{destination register, oprand register 1, oprand register 2} \\
\textbf{addi} & 0x1 & \textit{destination register, oprand register 1, immediate value} \\
\textbf{jmp} & 0x2 & \textit{jump address} \\
\textbf{mv} & 0x4 & \textit{destination register, source register} \\
 & 0x5 & \textit{destination memory address, source register} \\
\textit{} & 0x6 & \textit{destination register, source memory address} \\
 & 0x1 & \textit{destination memory address, source memory adress}
\end{tabular}
\caption{Instructions present in the ISA}
\label{tab:isa}
\end{table}

\subsubsection{Hardware design and implementation}
Based on the ISA, an architecture was designed which supported each of the outlined instructions. This first implementation design is illustrated schematically in figure \ref{fig:tst-arch}. 

\begin{figure}
    \centering
    \includegraphics[width=0.6\textwidth]{figures/simple_arch.png}
    \caption{[TEMPORARY FIGURE] Schematic diagram of the test architecture}
    \label{fig:tst-arch}
\end{figure}