# SPDX-License-Identifier: GPL-2.0
#
# Rockchip Clock specific Makefile
#

obj-y	+= clk.o
obj-y	+= clk-pll.o
obj-y	+= clk-cpu.o
obj-y	+= clk-half-divider.o
obj-y	+= clk-inverter.o
obj-y	+= clk-mmc-phase.o
obj-y	+= clk-muxgrf.o
obj-y	+= clk-ddr.o
obj-$(CONFIG_RESET_CONTROLLER)	+= softrst.o

obj-y	+= clk-px30.o
obj-y	+= clk-rv1108.o
obj-y	+= clk-rk3036.o
obj-y	+= clk-rk3128.o
obj-y	+= clk-rk3188.o
obj-y	+= clk-rk3228.o
obj-y	+= clk-rk3288.o
obj-y	+= clk-rk3308.o
obj-y	+= clk-rk3328.o
obj-y	+= clk-rk3368.o
obj-y	+= clk-rk3399.o
