
 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.37+34 (git sha1 80511ced7, clang 14.0.0-1ubuntu1.1 -fPIC -Os)


-- Executing script file `top.ys' --

1. Executing RTLIL frontend.
Input filename: top.il

2. Executing SYNTH_ICE40 pass.

2.1. Executing Verilog-2005 frontend: /opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v
Parsing Verilog input from `/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v' to AST representation.
Generating RTLIL representation for module `\SB_IO'.
Generating RTLIL representation for module `\SB_GB_IO'.
Generating RTLIL representation for module `\SB_GB'.
Generating RTLIL representation for module `\SB_LUT4'.
Generating RTLIL representation for module `\SB_CARRY'.
Generating RTLIL representation for module `\SB_DFF'.
Generating RTLIL representation for module `\SB_DFFE'.
Generating RTLIL representation for module `\SB_DFFSR'.
Generating RTLIL representation for module `\SB_DFFR'.
Generating RTLIL representation for module `\SB_DFFSS'.
Generating RTLIL representation for module `\SB_DFFS'.
Generating RTLIL representation for module `\SB_DFFESR'.
Generating RTLIL representation for module `\SB_DFFER'.
Generating RTLIL representation for module `\SB_DFFESS'.
Generating RTLIL representation for module `\SB_DFFES'.
Generating RTLIL representation for module `\SB_DFFN'.
Generating RTLIL representation for module `\SB_DFFNE'.
Generating RTLIL representation for module `\SB_DFFNSR'.
Generating RTLIL representation for module `\SB_DFFNR'.
Generating RTLIL representation for module `\SB_DFFNSS'.
Generating RTLIL representation for module `\SB_DFFNS'.
Generating RTLIL representation for module `\SB_DFFNESR'.
Generating RTLIL representation for module `\SB_DFFNER'.
Generating RTLIL representation for module `\SB_DFFNESS'.
Generating RTLIL representation for module `\SB_DFFNES'.
Generating RTLIL representation for module `\SB_RAM40_4K'.
Generating RTLIL representation for module `\SB_RAM40_4KNR'.
Generating RTLIL representation for module `\SB_RAM40_4KNW'.
Generating RTLIL representation for module `\SB_RAM40_4KNRNW'.
Generating RTLIL representation for module `\ICESTORM_LC'.
Generating RTLIL representation for module `\SB_PLL40_CORE'.
Generating RTLIL representation for module `\SB_PLL40_PAD'.
Generating RTLIL representation for module `\SB_PLL40_2_PAD'.
Generating RTLIL representation for module `\SB_PLL40_2F_CORE'.
Generating RTLIL representation for module `\SB_PLL40_2F_PAD'.
Generating RTLIL representation for module `\SB_WARMBOOT'.
Generating RTLIL representation for module `\SB_SPRAM256KA'.
Generating RTLIL representation for module `\SB_HFOSC'.
Generating RTLIL representation for module `\SB_LFOSC'.
Generating RTLIL representation for module `\SB_RGBA_DRV'.
Generating RTLIL representation for module `\SB_LED_DRV_CUR'.
Generating RTLIL representation for module `\SB_RGB_DRV'.
Generating RTLIL representation for module `\SB_I2C'.
Generating RTLIL representation for module `\SB_SPI'.
Generating RTLIL representation for module `\SB_LEDDA_IP'.
Generating RTLIL representation for module `\SB_FILTER_50NS'.
Generating RTLIL representation for module `\SB_IO_I3C'.
Generating RTLIL representation for module `\SB_IO_OD'.
Generating RTLIL representation for module `\SB_MAC16'.
Generating RTLIL representation for module `\ICESTORM_RAM'.
Successfully finished Verilog frontend.

2.2. Executing HIERARCHY pass (managing design hierarchy).

2.2.1. Analyzing design hierarchy..
Top module:  \top
Used module:     \top.pin_clk12_0
Used module:     \top.pin_led_0
Used module:     \top.cd_sync

2.2.2. Analyzing design hierarchy..
Top module:  \top
Used module:     \top.pin_clk12_0
Used module:     \top.pin_led_0
Used module:     \top.cd_sync
Removed 0 unused modules.

2.3. Executing PROC pass (convert processes to netlists).

2.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:1414$241 in module SB_DFFNES.
Marked 1 switch rules as full_case in process $proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:1353$234 in module SB_DFFNESS.
Marked 1 switch rules as full_case in process $proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:1273$230 in module SB_DFFNER.
Marked 1 switch rules as full_case in process $proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:1212$223 in module SB_DFFNESR.
Marked 1 switch rules as full_case in process $proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:1138$220 in module SB_DFFNS.
Marked 1 switch rules as full_case in process $proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:1088$217 in module SB_DFFNSS.
Marked 1 switch rules as full_case in process $proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:1017$214 in module SB_DFFNR.
Marked 1 switch rules as full_case in process $proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:967$211 in module SB_DFFNSR.
Marked 1 switch rules as full_case in process $proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:803$203 in module SB_DFFES.
Marked 1 switch rules as full_case in process $proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:742$196 in module SB_DFFESS.
Marked 1 switch rules as full_case in process $proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:662$192 in module SB_DFFER.
Marked 1 switch rules as full_case in process $proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:601$185 in module SB_DFFESR.
Marked 1 switch rules as full_case in process $proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:527$182 in module SB_DFFS.
Marked 1 switch rules as full_case in process $proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:477$179 in module SB_DFFSS.
Marked 1 switch rules as full_case in process $proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:406$176 in module SB_DFFR.
Marked 1 switch rules as full_case in process $proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:356$173 in module SB_DFFSR.
Marked 1 switch rules as full_case in process $group_1 in module top.
Marked 1 switch rules as full_case in process $group_2 in module top.cd_sync.
Removed a total of 0 dead cases.

2.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 12 redundant assignments.
Promoted 25 assignments to connections.

2.3.4. Executing PROC_INIT pass (extract init attributes).
Found init rule in `\SB_DFFNES.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:0$244'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFNESS.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:0$240'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFNER.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:0$233'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFNESR.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:0$229'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFNS.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:0$222'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFNSS.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:0$219'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFNR.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:0$216'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFNSR.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:0$213'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFNE.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:0$210'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFN.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:0$208'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFES.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:0$206'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFESS.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:0$202'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFER.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:0$195'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFESR.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:0$191'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFS.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:0$184'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFSS.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:0$181'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFR.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:0$178'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFSR.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:0$175'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFE.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:0$172'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFF.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:0$170'.
  Set init value: \Q = 1'0

2.3.5. Executing PROC_ARST pass (detect async resets in processes).
Found async reset \S in `\SB_DFFNES.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:1414$241'.
Found async reset \R in `\SB_DFFNER.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:1273$230'.
Found async reset \S in `\SB_DFFNS.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:1138$220'.
Found async reset \R in `\SB_DFFNR.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:1017$214'.
Found async reset \S in `\SB_DFFES.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:803$203'.
Found async reset \R in `\SB_DFFER.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:662$192'.
Found async reset \S in `\SB_DFFS.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:527$182'.
Found async reset \R in `\SB_DFFR.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:406$176'.

2.3.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~24 debug messages>

2.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\SB_DFFNES.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:0$244'.
Creating decoders for process `\SB_DFFNES.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:1414$241'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFNESS.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:0$240'.
Creating decoders for process `\SB_DFFNESS.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:1353$234'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFNER.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:0$233'.
Creating decoders for process `\SB_DFFNER.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:1273$230'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFNESR.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:0$229'.
Creating decoders for process `\SB_DFFNESR.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:1212$223'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFNS.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:0$222'.
Creating decoders for process `\SB_DFFNS.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:1138$220'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFNSS.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:0$219'.
Creating decoders for process `\SB_DFFNSS.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:1088$217'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFNR.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:0$216'.
Creating decoders for process `\SB_DFFNR.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:1017$214'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFNSR.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:0$213'.
Creating decoders for process `\SB_DFFNSR.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:967$211'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFNE.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:0$210'.
Creating decoders for process `\SB_DFFNE.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:922$209'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFN.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:0$208'.
Creating decoders for process `\SB_DFFN.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:882$207'.
Creating decoders for process `\SB_DFFES.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:0$206'.
Creating decoders for process `\SB_DFFES.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:803$203'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFESS.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:0$202'.
Creating decoders for process `\SB_DFFESS.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:742$196'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFER.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:0$195'.
Creating decoders for process `\SB_DFFER.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:662$192'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFESR.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:0$191'.
Creating decoders for process `\SB_DFFESR.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:601$185'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFS.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:0$184'.
Creating decoders for process `\SB_DFFS.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:527$182'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFSS.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:0$181'.
Creating decoders for process `\SB_DFFSS.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:477$179'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFR.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:0$178'.
Creating decoders for process `\SB_DFFR.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:406$176'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFSR.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:0$175'.
Creating decoders for process `\SB_DFFSR.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:356$173'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFE.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:0$172'.
Creating decoders for process `\SB_DFFE.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:311$171'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFF.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:0$170'.
Creating decoders for process `\SB_DFF.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:271$169'.
Creating decoders for process `\top.$group_1'.
     1/1: \timer$next
Creating decoders for process `\top.$group_0'.
     1/1: \pin_led_0_led_0__o$next
Creating decoders for process `\top.cd_sync.$group_4'.
Creating decoders for process `\top.cd_sync.$group_3'.
Creating decoders for process `\top.cd_sync.$group_2'.
     1/1: \timer$next
Creating decoders for process `\top.cd_sync.$group_1'.
     1/1: \ready$next
Creating decoders for process `\top.cd_sync.$group_0'.

2.3.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.3.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\SB_DFFNES.\Q' using process `\SB_DFFNES.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:1414$241'.
  created $adff cell `$procdff$439' with negative edge clock and positive level reset.
Creating register for signal `\SB_DFFNESS.\Q' using process `\SB_DFFNESS.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:1353$234'.
  created $dff cell `$procdff$440' with negative edge clock.
Creating register for signal `\SB_DFFNER.\Q' using process `\SB_DFFNER.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:1273$230'.
  created $adff cell `$procdff$441' with negative edge clock and positive level reset.
Creating register for signal `\SB_DFFNESR.\Q' using process `\SB_DFFNESR.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:1212$223'.
  created $dff cell `$procdff$442' with negative edge clock.
Creating register for signal `\SB_DFFNS.\Q' using process `\SB_DFFNS.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:1138$220'.
  created $adff cell `$procdff$443' with negative edge clock and positive level reset.
Creating register for signal `\SB_DFFNSS.\Q' using process `\SB_DFFNSS.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:1088$217'.
  created $dff cell `$procdff$444' with negative edge clock.
Creating register for signal `\SB_DFFNR.\Q' using process `\SB_DFFNR.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:1017$214'.
  created $adff cell `$procdff$445' with negative edge clock and positive level reset.
Creating register for signal `\SB_DFFNSR.\Q' using process `\SB_DFFNSR.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:967$211'.
  created $dff cell `$procdff$446' with negative edge clock.
Creating register for signal `\SB_DFFNE.\Q' using process `\SB_DFFNE.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:922$209'.
  created $dff cell `$procdff$447' with negative edge clock.
Creating register for signal `\SB_DFFN.\Q' using process `\SB_DFFN.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:882$207'.
  created $dff cell `$procdff$448' with negative edge clock.
Creating register for signal `\SB_DFFES.\Q' using process `\SB_DFFES.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:803$203'.
  created $adff cell `$procdff$449' with positive edge clock and positive level reset.
Creating register for signal `\SB_DFFESS.\Q' using process `\SB_DFFESS.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:742$196'.
  created $dff cell `$procdff$450' with positive edge clock.
Creating register for signal `\SB_DFFER.\Q' using process `\SB_DFFER.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:662$192'.
  created $adff cell `$procdff$451' with positive edge clock and positive level reset.
Creating register for signal `\SB_DFFESR.\Q' using process `\SB_DFFESR.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:601$185'.
  created $dff cell `$procdff$452' with positive edge clock.
Creating register for signal `\SB_DFFS.\Q' using process `\SB_DFFS.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:527$182'.
  created $adff cell `$procdff$453' with positive edge clock and positive level reset.
Creating register for signal `\SB_DFFSS.\Q' using process `\SB_DFFSS.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:477$179'.
  created $dff cell `$procdff$454' with positive edge clock.
Creating register for signal `\SB_DFFR.\Q' using process `\SB_DFFR.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:406$176'.
  created $adff cell `$procdff$455' with positive edge clock and positive level reset.
Creating register for signal `\SB_DFFSR.\Q' using process `\SB_DFFSR.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:356$173'.
  created $dff cell `$procdff$456' with positive edge clock.
Creating register for signal `\SB_DFFE.\Q' using process `\SB_DFFE.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:311$171'.
  created $dff cell `$procdff$457' with positive edge clock.
Creating register for signal `\SB_DFF.\Q' using process `\SB_DFF.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:271$169'.
  created $dff cell `$procdff$458' with positive edge clock.

2.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `SB_DFFNES.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:0$244'.
Found and cleaned up 1 empty switch in `\SB_DFFNES.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:1414$241'.
Removing empty process `SB_DFFNES.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:1414$241'.
Removing empty process `SB_DFFNESS.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:0$240'.
Found and cleaned up 2 empty switches in `\SB_DFFNESS.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:1353$234'.
Removing empty process `SB_DFFNESS.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:1353$234'.
Removing empty process `SB_DFFNER.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:0$233'.
Found and cleaned up 1 empty switch in `\SB_DFFNER.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:1273$230'.
Removing empty process `SB_DFFNER.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:1273$230'.
Removing empty process `SB_DFFNESR.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:0$229'.
Found and cleaned up 2 empty switches in `\SB_DFFNESR.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:1212$223'.
Removing empty process `SB_DFFNESR.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:1212$223'.
Removing empty process `SB_DFFNS.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:0$222'.
Removing empty process `SB_DFFNS.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:1138$220'.
Removing empty process `SB_DFFNSS.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:0$219'.
Found and cleaned up 1 empty switch in `\SB_DFFNSS.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:1088$217'.
Removing empty process `SB_DFFNSS.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:1088$217'.
Removing empty process `SB_DFFNR.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:0$216'.
Removing empty process `SB_DFFNR.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:1017$214'.
Removing empty process `SB_DFFNSR.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:0$213'.
Found and cleaned up 1 empty switch in `\SB_DFFNSR.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:967$211'.
Removing empty process `SB_DFFNSR.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:967$211'.
Removing empty process `SB_DFFNE.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:0$210'.
Found and cleaned up 1 empty switch in `\SB_DFFNE.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:922$209'.
Removing empty process `SB_DFFNE.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:922$209'.
Removing empty process `SB_DFFN.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:0$208'.
Removing empty process `SB_DFFN.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:882$207'.
Removing empty process `SB_DFFES.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:0$206'.
Found and cleaned up 1 empty switch in `\SB_DFFES.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:803$203'.
Removing empty process `SB_DFFES.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:803$203'.
Removing empty process `SB_DFFESS.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:0$202'.
Found and cleaned up 2 empty switches in `\SB_DFFESS.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:742$196'.
Removing empty process `SB_DFFESS.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:742$196'.
Removing empty process `SB_DFFER.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:0$195'.
Found and cleaned up 1 empty switch in `\SB_DFFER.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:662$192'.
Removing empty process `SB_DFFER.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:662$192'.
Removing empty process `SB_DFFESR.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:0$191'.
Found and cleaned up 2 empty switches in `\SB_DFFESR.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:601$185'.
Removing empty process `SB_DFFESR.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:601$185'.
Removing empty process `SB_DFFS.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:0$184'.
Removing empty process `SB_DFFS.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:527$182'.
Removing empty process `SB_DFFSS.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:0$181'.
Found and cleaned up 1 empty switch in `\SB_DFFSS.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:477$179'.
Removing empty process `SB_DFFSS.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:477$179'.
Removing empty process `SB_DFFR.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:0$178'.
Removing empty process `SB_DFFR.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:406$176'.
Removing empty process `SB_DFFSR.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:0$175'.
Found and cleaned up 1 empty switch in `\SB_DFFSR.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:356$173'.
Removing empty process `SB_DFFSR.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:356$173'.
Removing empty process `SB_DFFE.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:0$172'.
Found and cleaned up 1 empty switch in `\SB_DFFE.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:311$171'.
Removing empty process `SB_DFFE.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:311$171'.
Removing empty process `SB_DFF.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:0$170'.
Removing empty process `SB_DFF.$proc$/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:271$169'.
Found and cleaned up 2 empty switches in `\top.$group_1'.
Removing empty process `top.$group_1'.
Found and cleaned up 2 empty switches in `\top.$group_0'.
Removing empty process `top.$group_0'.
Removing empty process `top.cd_sync.$group_4'.
Removing empty process `top.cd_sync.$group_3'.
Found and cleaned up 1 empty switch in `\top.cd_sync.$group_2'.
Removing empty process `top.cd_sync.$group_2'.
Found and cleaned up 1 empty switch in `\top.cd_sync.$group_1'.
Removing empty process `top.cd_sync.$group_1'.
Removing empty process `top.cd_sync.$group_0'.
Cleaned up 24 empty switches.

2.3.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
Optimizing module top.pin_clk12_0.
Optimizing module top.pin_led_0.
Optimizing module top.cd_sync.

2.4. Executing FLATTEN pass (flatten design).
Deleting now unused module top.pin_clk12_0.
Deleting now unused module top.pin_led_0.
Deleting now unused module top.cd_sync.
<suppressed ~3 debug messages>

2.5. Executing TRIBUF pass.

2.6. Executing DEMINOUT pass (demote inout ports to input or output).

2.7. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~2 debug messages>

2.8. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 1 unused cells and 15 unused wires.
<suppressed ~4 debug messages>

2.9. Executing CHECK pass (checking for obvious problems).
Checking module top...
Found and reported 0 problems.

2.10. Executing OPT pass (performing simple optimizations).

2.10.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

2.10.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.

2.10.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~4 debug messages>

2.10.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

2.10.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

2.10.6. Executing OPT_DFF pass (perform DFF optimizations).

2.10.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 2 unused wires.
<suppressed ~1 debug messages>

2.10.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

2.10.9. Rerunning OPT passes. (Maybe there is more to do..)

2.10.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~4 debug messages>

2.10.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

2.10.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

2.10.13. Executing OPT_DFF pass (perform DFF optimizations).

2.10.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

2.10.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

2.10.16. Finished OPT passes. (There is nothing left to do.)

2.11. Executing FSM pass (extract and optimize FSM).

2.11.1. Executing FSM_DETECT pass (finding FSMs in design).

2.11.2. Executing FSM_EXTRACT pass (extracting FSM from design).

2.11.3. Executing FSM_OPT pass (simple optimizations of FSMs).

2.11.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

2.11.5. Executing FSM_OPT pass (simple optimizations of FSMs).

2.11.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).

2.11.7. Executing FSM_INFO pass (dumping all available information on FSM cells).

2.11.8. Executing FSM_MAP pass (mapping FSMs to basic logic).

2.12. Executing OPT pass (performing simple optimizations).

2.12.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

2.12.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

2.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~4 debug messages>

2.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

2.12.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

2.12.6. Executing OPT_DFF pass (perform DFF optimizations).
Adding EN signal on $flatten\cd_sync.$11 ($dff) from module top (D = $flatten\cd_sync.$5 [7:0], Q = \cd_sync.timer).
Adding EN signal on $flatten\cd_sync.$10 ($dff) from module top (D = 1'1, Q = \cd_sync.ready).
Adding SRST signal on $11 ($dff) from module top (D = $7 [22:0], Q = \timer, rval = 23'00000000000000000000000).
Adding SRST signal on $10 ($dff) from module top (D = $procmux$430_Y, Q = \pin_led_0_led_0__o, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$466 ($sdff) from module top (D = $3, Q = \pin_led_0_led_0__o).

2.12.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 6 unused cells and 6 unused wires.
<suppressed ~11 debug messages>

2.12.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

2.12.9. Rerunning OPT passes. (Maybe there is more to do..)

2.12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

2.12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

2.12.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

2.12.13. Executing OPT_DFF pass (perform DFF optimizations).

2.12.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

2.12.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

2.12.16. Finished OPT passes. (There is nothing left to do.)

2.13. Executing WREDUCE pass (reducing word size of cells).
Removed top 1 bits (of 24) from port Y of cell top.$9 ($add).
Removed top 1 bits (of 9) from port Y of cell top.$flatten\cd_sync.$7 ($add).
Removed top 1 bits (of 24) from wire top.$7.
Removed top 1 bits (of 9) from wire top.$flatten\cd_sync.$5.

2.14. Executing PEEPOPT pass (run peephole optimizers).

2.15. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 2 unused wires.
<suppressed ~1 debug messages>

2.16. Executing SHARE pass (SAT-based resource sharing).

2.17. Executing TECHMAP pass (map to technology primitives).

2.17.1. Executing Verilog-2005 frontend: /opt/oss-cad-suite/lib/../share/yosys/cmp2lut.v
Parsing Verilog input from `/opt/oss-cad-suite/lib/../share/yosys/cmp2lut.v' to AST representation.
Generating RTLIL representation for module `\_90_lut_cmp_'.
Successfully finished Verilog frontend.

2.17.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~6 debug messages>

2.18. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

2.19. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

2.20. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module top:
  creating $macc model for $9 ($add).
  creating $macc model for $flatten\cd_sync.$7 ($add).
  creating $alu model for $macc $flatten\cd_sync.$7.
  creating $alu model for $macc $9.
  creating $alu cell for $9: $auto$alumacc.cc:485:replace_alu$471
  creating $alu cell for $flatten\cd_sync.$7: $auto$alumacc.cc:485:replace_alu$474
  created 2 $alu and 0 $macc cells.

2.21. Executing OPT pass (performing simple optimizations).

2.21.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

2.21.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

2.21.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

2.21.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

2.21.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

2.21.6. Executing OPT_DFF pass (perform DFF optimizations).

2.21.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

2.21.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

2.21.9. Finished OPT passes. (There is nothing left to do.)

2.22. Executing MEMORY pass.

2.22.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.

2.22.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
Performed a total of 0 transformations.

2.22.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).

2.22.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).

2.22.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).

2.22.6. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

2.22.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).

2.22.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
Performed a total of 0 transformations.

2.22.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

2.22.10. Executing MEMORY_COLLECT pass (generating $mem cells).

2.23. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

2.24. Executing MEMORY_LIBMAP pass (mapping memories to cells).

2.25. Executing TECHMAP pass (map to technology primitives).

2.25.1. Executing Verilog-2005 frontend: /opt/oss-cad-suite/lib/../share/yosys/ice40/brams_map.v
Parsing Verilog input from `/opt/oss-cad-suite/lib/../share/yosys/ice40/brams_map.v' to AST representation.
Generating RTLIL representation for module `\$__ICE40_RAM4K_'.
Successfully finished Verilog frontend.

2.25.2. Executing Verilog-2005 frontend: /opt/oss-cad-suite/lib/../share/yosys/ice40/spram_map.v
Parsing Verilog input from `/opt/oss-cad-suite/lib/../share/yosys/ice40/spram_map.v' to AST representation.
Generating RTLIL representation for module `\$__ICE40_SPRAM_'.
Successfully finished Verilog frontend.

2.25.3. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~4 debug messages>

2.26. Executing ICE40_BRAMINIT pass.

2.27. Executing OPT pass (performing simple optimizations).

2.27.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

2.27.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

2.27.3. Executing OPT_DFF pass (perform DFF optimizations).

2.27.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

2.27.5. Finished fast OPT passes.

2.28. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).

2.29. Executing OPT pass (performing simple optimizations).

2.29.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

2.29.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

2.29.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

2.29.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

2.29.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

2.29.6. Executing OPT_DFF pass (perform DFF optimizations).

2.29.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

2.29.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

2.29.9. Finished OPT passes. (There is nothing left to do.)

2.30. Executing ICE40_WRAPCARRY pass (wrap carries).

2.31. Executing TECHMAP pass (map to technology primitives).

2.31.1. Executing Verilog-2005 frontend: /opt/oss-cad-suite/lib/../share/yosys/techmap.v
Parsing Verilog input from `/opt/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

2.31.2. Executing Verilog-2005 frontend: /opt/oss-cad-suite/lib/../share/yosys/ice40/arith_map.v
Parsing Verilog input from `/opt/oss-cad-suite/lib/../share/yosys/ice40/arith_map.v' to AST representation.
Generating RTLIL representation for module `\_80_ice40_alu'.
Successfully finished Verilog frontend.

2.31.3. Continuing TECHMAP pass.
Using extmapper simplemap for cells of type $reduce_or.
Using extmapper simplemap for cells of type $eq.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $dffe.
Using template $paramod$c3cd1564c35d873179656addd6052d7ea8b6d991\_80_ice40_alu for cells of type $alu.
Using extmapper simplemap for cells of type $sdffe.
Using template $paramod$36fdbc18fab0758c8553dda57bd33e3f8f3e8765\_80_ice40_alu for cells of type $alu.
Using extmapper simplemap for cells of type $sdff.
Using extmapper simplemap for cells of type $xor.
Using extmapper simplemap for cells of type $mux.
Using extmapper simplemap for cells of type $pos.
No more expansions possible.
<suppressed ~132 debug messages>

2.32. Executing OPT pass (performing simple optimizations).

2.32.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~103 debug messages>

2.32.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~48 debug messages>
Removed a total of 16 cells.

2.32.3. Executing OPT_DFF pass (perform DFF optimizations).

2.32.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 18 unused cells and 40 unused wires.
<suppressed ~19 debug messages>

2.32.5. Finished fast OPT passes.

2.33. Executing ICE40_OPT pass (performing simple optimizations).

2.33.1. Running ICE40 specific optimizations.
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$471.slice[0].carry: CO=\timer [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$474.slice[0].carry: CO=\cd_sync.timer [0]

2.33.2. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

2.33.3. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

2.33.4. Executing OPT_DFF pass (perform DFF optimizations).

2.33.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

2.33.6. Rerunning OPT passes. (Removed registers in this run.)

2.33.7. Running ICE40 specific optimizations.

2.33.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

2.33.9. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

2.33.10. Executing OPT_DFF pass (perform DFF optimizations).

2.33.11. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

2.33.12. Finished OPT passes. (There is nothing left to do.)

2.34. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).

2.35. Executing TECHMAP pass (map to technology primitives).

2.35.1. Executing Verilog-2005 frontend: /opt/oss-cad-suite/lib/../share/yosys/ice40/ff_map.v
Parsing Verilog input from `/opt/oss-cad-suite/lib/../share/yosys/ice40/ff_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_SDFFCE_NP0P_'.
Generating RTLIL representation for module `\$_SDFFCE_NP1P_'.
Generating RTLIL representation for module `\$_SDFFCE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFCE_PP1P_'.
Successfully finished Verilog frontend.

2.35.2. Continuing TECHMAP pass.
Using template \$_DFFE_PP_ for cells of type $_DFFE_PP_.
Using template \$_SDFF_PP0_ for cells of type $_SDFF_PP0_.
Using template \$_SDFFCE_PP0P_ for cells of type $_SDFFCE_PP0P_.
No more expansions possible.
<suppressed ~55 debug messages>

2.36. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

2.37. Executing SIMPLEMAP pass (map simple cells to gate primitives).
Mapping top.$auto$alumacc.cc:485:replace_alu$474.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$471.slice[0].carry ($lut).

2.38. Executing ICE40_OPT pass (performing simple optimizations).

2.38.1. Running ICE40 specific optimizations.

2.38.2. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~28 debug messages>

2.38.3. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~3 debug messages>
Removed a total of 1 cells.

2.38.4. Executing OPT_DFF pass (perform DFF optimizations).

2.38.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 175 unused wires.
<suppressed ~1 debug messages>

2.38.6. Rerunning OPT passes. (Removed registers in this run.)

2.38.7. Running ICE40 specific optimizations.

2.38.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

2.38.9. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

2.38.10. Executing OPT_DFF pass (perform DFF optimizations).

2.38.11. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

2.38.12. Finished OPT passes. (There is nothing left to do.)

2.39. Executing TECHMAP pass (map to technology primitives).

2.39.1. Executing Verilog-2005 frontend: /opt/oss-cad-suite/lib/../share/yosys/ice40/latches_map.v
Parsing Verilog input from `/opt/oss-cad-suite/lib/../share/yosys/ice40/latches_map.v' to AST representation.
Generating RTLIL representation for module `\$_DLATCH_N_'.
Generating RTLIL representation for module `\$_DLATCH_P_'.
Successfully finished Verilog frontend.

2.39.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~4 debug messages>

2.40. Executing Verilog-2005 frontend: /opt/oss-cad-suite/lib/../share/yosys/ice40/abc9_model.v
Parsing Verilog input from `/opt/oss-cad-suite/lib/../share/yosys/ice40/abc9_model.v' to AST representation.
Generating RTLIL representation for module `$__ICE40_CARRY_WRAPPER'.
Successfully finished Verilog frontend.

2.41. Executing ABC9 pass.

2.41.1. Executing ABC9_OPS pass (helper functions for ABC9).

2.41.2. Executing ABC9_OPS pass (helper functions for ABC9).

2.41.3. Executing SCC pass (detecting logic loops).
Found 0 SCCs in module top.
Found 0 SCCs.

2.41.4. Executing ABC9_OPS pass (helper functions for ABC9).

2.41.5. Executing PROC pass (convert processes to netlists).

2.41.5.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.41.5.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.41.5.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.

2.41.5.4. Executing PROC_INIT pass (extract init attributes).

2.41.5.5. Executing PROC_ARST pass (detect async resets in processes).

2.41.5.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

2.41.5.7. Executing PROC_MUX pass (convert decision trees to multiplexers).

2.41.5.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.41.5.9. Executing PROC_DFF pass (convert process syncs to FFs).

2.41.5.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.41.5.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.41.5.12. Executing OPT_EXPR pass (perform const folding).

2.41.6. Executing TECHMAP pass (map to technology primitives).

2.41.6.1. Executing Verilog-2005 frontend: /opt/oss-cad-suite/lib/../share/yosys/techmap.v
Parsing Verilog input from `/opt/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

2.41.6.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~126 debug messages>

2.41.7. Executing OPT pass (performing simple optimizations).

2.41.7.1. Executing OPT_EXPR pass (perform const folding).

2.41.7.2. Executing OPT_MERGE pass (detect identical cells).
Removed a total of 0 cells.

2.41.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Removed 0 multiplexer ports.

2.41.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Performed a total of 0 changes.

2.41.7.5. Executing OPT_MERGE pass (detect identical cells).
Removed a total of 0 cells.

2.41.7.6. Executing OPT_DFF pass (perform DFF optimizations).

2.41.7.7. Executing OPT_CLEAN pass (remove unused cells and wires).

2.41.7.8. Executing OPT_EXPR pass (perform const folding).

2.41.7.9. Finished OPT passes. (There is nothing left to do.)

2.41.8. Executing TECHMAP pass (map to technology primitives).

2.41.8.1. Executing Verilog-2005 frontend: /opt/oss-cad-suite/lib/../share/yosys/abc9_map.v
Parsing Verilog input from `/opt/oss-cad-suite/lib/../share/yosys/abc9_map.v' to AST representation.
Successfully finished Verilog frontend.

2.41.8.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~2 debug messages>

2.41.9. Executing Verilog-2005 frontend: /opt/oss-cad-suite/lib/../share/yosys/abc9_model.v
Parsing Verilog input from `/opt/oss-cad-suite/lib/../share/yosys/abc9_model.v' to AST representation.
Generating RTLIL representation for module `$__ABC9_DELAY'.
Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'.
Generating RTLIL representation for module `$__DFF_N__$abc9_flop'.
Generating RTLIL representation for module `$__DFF_P__$abc9_flop'.
Successfully finished Verilog frontend.

2.41.10. Executing ABC9_OPS pass (helper functions for ABC9).
<suppressed ~59 debug messages>

2.41.11. Executing ABC9_OPS pass (helper functions for ABC9).

2.41.12. Executing ABC9_OPS pass (helper functions for ABC9).
<suppressed ~2 debug messages>

2.41.13. Executing TECHMAP pass (map to technology primitives).

2.41.13.1. Executing Verilog-2005 frontend: /opt/oss-cad-suite/lib/../share/yosys/techmap.v
Parsing Verilog input from `/opt/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

2.41.13.2. Continuing TECHMAP pass.
Using template $paramod$__ICE40_CARRY_WRAPPER\LUT=16'0110100110010110\I3_IS_CI=1'1 for cells of type $paramod$__ICE40_CARRY_WRAPPER\LUT=16'0110100110010110\I3_IS_CI=1'1.
Using template $paramod\SB_LUT4\LUT_INIT=16'0110100110010110 for cells of type SB_LUT4.
Using template SB_CARRY for cells of type SB_CARRY.
Using extmapper simplemap for cells of type $mux.
Using extmapper simplemap for cells of type $logic_and.
Using extmapper simplemap for cells of type $logic_or.
No more expansions possible.
<suppressed ~147 debug messages>

2.41.14. Executing OPT pass (performing simple optimizations).

2.41.14.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~4 debug messages>

2.41.14.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~29 debug messages>
Removed a total of 12 cells.

2.41.14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

2.41.14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

2.41.14.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

2.41.14.6. Executing OPT_DFF pass (perform DFF optimizations).

2.41.14.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 24 unused wires.
<suppressed ~1 debug messages>

2.41.14.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

2.41.14.9. Rerunning OPT passes. (Maybe there is more to do..)

2.41.14.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

2.41.14.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

2.41.14.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

2.41.14.13. Executing OPT_DFF pass (perform DFF optimizations).

2.41.14.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

2.41.14.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

2.41.14.16. Finished OPT passes. (There is nothing left to do.)

2.41.15. Executing AIGMAP pass (map logic to AIG).
Module top: replaced 7 cells with 43 new cells, skipped 11 cells.
  replaced 2 cell types:
       2 $_OR_
       5 $_MUX_
  not replaced 3 cell types:
       8 $specify2
       1 $_NOT_
       2 $_AND_

2.41.16. Executing AIGMAP pass (map logic to AIG).
Module top: replaced 30 cells with 120 new cells, skipped 143 cells.
  replaced 1 cell types:
      30 $_OR_
  not replaced 10 cell types:
      21 $_NOT_
       1 $_AND_
      29 $paramod$__ICE40_CARRY_WRAPPER\LUT=16'0110100110010110\I3_IS_CI=1'1
       1 SB_IO
       1 SB_GB_IO
       9 SB_DFFE
      23 SB_DFFSR
       1 SB_DFFESR
      24 $paramod$__ABC9_DELAY\DELAY=32'00000000000000000000000011001011
      33 $paramod$__ABC9_DELAY\DELAY=32'00000000000000000000000000010101

2.41.16.1. Executing ABC9_OPS pass (helper functions for ABC9).

2.41.16.2. Executing ABC9_OPS pass (helper functions for ABC9).

2.41.16.3. Executing XAIGER backend.
<suppressed ~44 debug messages>
Extracted 31 AND gates and 298 wires from module `top' to a netlist network with 36 inputs and 64 outputs.

2.41.16.4. Executing ABC9_EXE pass (technology mapping using ABC9).

2.41.16.5. Executing ABC9.
Running ABC command: "<yosys-exe-dir>/yosys-abc" -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
ABC: 
ABC: + read_lut <abc-temp-dir>/input.lut 
ABC: + read_box <abc-temp-dir>/input.box 
ABC: + &read <abc-temp-dir>/input.xaig 
ABC: + &ps 
ABC: <abc-temp-dir>/input : i/o =     36/     64  and =      30  lev =    6 (0.56)  mem = 0.01 MB  box = 86  bb = 57
ABC: + &scorr 
ABC: Warning: The network is combinational.
ABC: + &sweep 
ABC: + &dc2 
ABC: + &dch -f 
ABC: + &ps 
ABC: <abc-temp-dir>/input : i/o =     36/     64  and =      60  lev =    6 (0.56)  mem = 0.01 MB  ch =    6  box = 86  bb = 57
ABC: + &if -W 250 -v 
ABC: K = 4. Memory (bytes): Truth =    0. Cut =   48. Obj =  128. Set =  528. CutMin = no
ABC: Node =      60.  Ch =     6.  Total mem =    0.07 MB. Peak cut mem =    0.00 MB.
ABC: P:  Del = 3628.00.  Ar =      13.0.  Edge =       43.  Cut =      212.  T =     0.00 sec
ABC: P:  Del = 3628.00.  Ar =      13.0.  Edge =       43.  Cut =      212.  T =     0.00 sec
ABC: P:  Del = 3628.00.  Ar =      11.0.  Edge =       41.  Cut =      219.  T =     0.00 sec
ABC: F:  Del = 3628.00.  Ar =      11.0.  Edge =       41.  Cut =      214.  T =     0.00 sec
ABC: A:  Del = 3628.00.  Ar =      11.0.  Edge =       41.  Cut =      202.  T =     0.00 sec
ABC: A:  Del = 3628.00.  Ar =      11.0.  Edge =       41.  Cut =      202.  T =     0.00 sec
ABC: Total time =     0.00 sec
ABC: + &write -n <abc-temp-dir>/output.aig 
ABC: + &mfs 
ABC: The network is not changed by "&mfs".
ABC: + &ps -l 
ABC: <abc-temp-dir>/input : i/o =     36/     64  and =      30  lev =    6 (0.56)  mem = 0.01 MB  box = 86  bb = 57
ABC: Mapping (K=4)  :  lut =     11  edge =      41  lev =    4 (0.38)  levB =   23  mem = 0.00 MB
ABC: LUT = 11 : 2=1 9.1 %  3=1 9.1 %  4=9 81.8 %  Ave = 3.73
ABC: + &write -n <abc-temp-dir>/output.aig 
ABC: + time 
ABC: elapse: 0.01 seconds, total: 0.01 seconds

2.41.16.6. Executing AIGER frontend.
<suppressed ~212 debug messages>
Removed 35 unused cells and 452 unused wires.

2.41.16.7. Executing ABC9_OPS pass (helper functions for ABC9).
ABC RESULTS:              $lut cells:       15
ABC RESULTS:   $paramod$__ICE40_CARRY_WRAPPER\LUT=16'0110100110010110\I3_IS_CI=1'1 cells:       29
ABC RESULTS:           input signals:        4
ABC RESULTS:          output signals:       64
Removing temp directory.

2.41.17. Executing TECHMAP pass (map to technology primitives).

2.41.17.1. Executing Verilog-2005 frontend: /opt/oss-cad-suite/lib/../share/yosys/abc9_unmap.v
Parsing Verilog input from `/opt/oss-cad-suite/lib/../share/yosys/abc9_unmap.v' to AST representation.
Generating RTLIL representation for module `\$__DFF_x__$abc9_flop'.
Generating RTLIL representation for module `\$__ABC9_SCC_BREAKER'.
Successfully finished Verilog frontend.

2.41.17.2. Continuing TECHMAP pass.
Using template $paramod$__ICE40_CARRY_WRAPPER\LUT=16'0110100110010110\I3_IS_CI=1'1 for cells of type $paramod$__ICE40_CARRY_WRAPPER\LUT=16'0110100110010110\I3_IS_CI=1'1.
No more expansions possible.
<suppressed ~35 debug messages>

2.42. Executing ICE40_WRAPCARRY pass (wrap carries).

2.43. Executing TECHMAP pass (map to technology primitives).

2.43.1. Executing Verilog-2005 frontend: /opt/oss-cad-suite/lib/../share/yosys/ice40/ff_map.v
Parsing Verilog input from `/opt/oss-cad-suite/lib/../share/yosys/ice40/ff_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_SDFFCE_NP0P_'.
Generating RTLIL representation for module `\$_SDFFCE_NP1P_'.
Generating RTLIL representation for module `\$_SDFFCE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFCE_PP1P_'.
Successfully finished Verilog frontend.

2.43.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~22 debug messages>
Removed 3 unused cells and 516 unused wires.

2.44. Executing OPT_LUT pass (optimize LUTs).
Discovering LUTs.
Number of LUTs:       45
  1-LUT                4
  2-LUT                4
  3-LUT               28
  4-LUT                9
  with \SB_CARRY    (#0)   27
  with \SB_CARRY    (#1)   27

Eliminating LUTs.
Number of LUTs:       45
  1-LUT                4
  2-LUT                4
  3-LUT               28
  4-LUT                9
  with \SB_CARRY    (#0)   27
  with \SB_CARRY    (#1)   27

Combining LUTs.
Number of LUTs:       45
  1-LUT                4
  2-LUT                4
  3-LUT               28
  4-LUT                9
  with \SB_CARRY    (#0)   27
  with \SB_CARRY    (#1)   27

Eliminated 0 LUTs.
Combined 0 LUTs.
<suppressed ~207 debug messages>

2.45. Executing TECHMAP pass (map to technology primitives).

2.45.1. Executing Verilog-2005 frontend: /opt/oss-cad-suite/lib/../share/yosys/ice40/cells_map.v
Parsing Verilog input from `/opt/oss-cad-suite/lib/../share/yosys/ice40/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$lut'.
Successfully finished Verilog frontend.

2.45.2. Continuing TECHMAP pass.
Using template $paramod$fd904e9e35cfd343a9df248824bd3f1408724879\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut.
Using template $paramod$364c9ffbffac467d60dfec81bba4e18476c15602\$lut for cells of type $lut.
Using template $paramod$5e9374f44a27c3f8a1c38af244ec43ceb4fb8d4f\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut.
Using template $paramod$30305e55a780880b9c824fe3509a4d981acb0f2b\$lut for cells of type $lut.
Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8\$lut for cells of type $lut.
Using template $paramod$a5516fc31d1e552de2435200bb732b4d4ad63a9c\$lut for cells of type $lut.
Using template $paramod$6e238df02989b317f10820a22773676e71120644\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut.
Using template $paramod$5307f40f1b453046eb68ee1a10c3f82d605af6fc\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0111 for cells of type $lut.
No more expansions possible.
<suppressed ~204 debug messages>
Removed 0 unused cells and 94 unused wires.

2.46. Executing AUTONAME pass.
Renamed 420 objects in module top (12 iterations).
<suppressed ~173 debug messages>

2.47. Executing HIERARCHY pass (managing design hierarchy).

2.47.1. Analyzing design hierarchy..
Top module:  \top

2.47.2. Analyzing design hierarchy..
Top module:  \top
Removed 0 unused modules.

2.48. Printing statistics.

=== top ===

   Number of wires:                 83
   Number of wire bits:            124
   Number of public wires:          83
   Number of public wire bits:     124
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                107
     SB_CARRY                       27
     SB_DFFE                         9
     SB_DFFESR                       1
     SB_DFFSR                       23
     SB_GB_IO                        1
     SB_IO                           1
     SB_LUT4                        45

2.49. Executing CHECK pass (checking for obvious problems).
Checking module top...
Found and reported 0 problems.

3. Executing JSON backend.

End of script. Logfile hash: 3e790fba52, CPU: user 0.51s system 0.02s, MEM: 27.75 MB peak
Yosys 0.37+34 (git sha1 80511ced7, clang 14.0.0-1ubuntu1.1 -fPIC -Os)
Time spent: 62% 19x read_verilog (0 sec), 7% 1x abc9_exe (0 sec), ...
