`default_nettype none

module SOC (
    input CLK,
    input RST,
    output [4:0] LEDS,
    output irda_TXD,
    output irda_SD
);
  reg [31:0] clkctr = 0;

  always @(posedge CLK) begin
      clkctr <= clkctr + 1;
  end

  assign LEDS = 0;
  assign irda_TXD = clkctr[13] * clkctr[21];
  assign irda_SD  = 0;
endmodule
