`default_nettype none

module SOC (
    input CLK,
    input RST,
    output [4:0] LEDS,
    input RXD,
    output TXD,
    output PMOD1,
    output PMOD2,
    output PMOD3
);
  reg [4:0] count = 5'b11111;
  reg [31:0] clkctr = 0;

  always @(posedge CLK) begin
      clkctr <= clkctr + 1;
  end

  assign PMOD1 = CLK;
  assign PMOD2 = clkctr[0];
  assign PMOD3 = clkctr[1];
  assign LEDS = clkctr[27:23] * (clkctr[21] | CLK);
  assign TXD = 1'b0;
endmodule
